Memory arrays typically comprise a plurality of memory cells, each storing one bit of data. To read the data in a cell, addressing signals are provided to it and the resultant voltage level is provided to output devices which convert the voltage to one of two predetermined levels indicating either a "1" or a "0".
Reference is now briefly made to FIG. 1A which illustrates a basic output device. The output device includes a p-channel transistor 1, connected between an output line OUT and a Vcc internal supply, and an n-channel transistor 3 connected between the output line OUT and a Vss ground supply. The output line OUT typically has a load 5 on it, represented in FIG. 1A by a capacitor.
A control signal, representing the data read from the memory cell, is provided to the gates G of the two transistors. In response, one of the transistors is activated and the other is deactivated. If the p-channel transistor 1 is activated, it pulls the output line OUT towards the Vcc supply voltage. If the n-channel transistor 3 is activated, it pulls the output line OUT towards the Vss ground supply voltage.
Typically, the load 5 is formed of many processing devices, such as integrated circuit chips, which are connected to the output device via a bus and which access the memory array whenever they need the data stored therein. A bus, due to its large capacitance, is a large load. Since it is desired to read data from the memory arrays quickly, the output devices often have to switch values quickly which is achieved by supplying high currents to the output devices.
Unfortunately, the fast switching generates noise on the supply voltage Vss of the output device, where the noise V.sub.-- N is generated due to the inductance L of the bus and of the processing devices (e.g. the "package") and is described by: EQU V.sub.-- N=L*di/dt (1)
where i is the current and di/dt is the speed at which the current changes.
The noise is especially problematic if the output signal is provided as an input signal to a transistor logic (TTL) device. TTL devices have an industry standardized allowed input voltage range from 0.8 V to 2.0 V between which their input signal must remain. The TTL devices then compare this to the ground supply voltage Vss to determine whether they received a "1" or a "0" indication.
If the high end of the range, known as V.sub.1H and indicating a "1", is solidly at 2.0 V and the supply voltage Vss of the memory array should be at 0.0 V but, due to the noise V.sub.13 N on the supply voltage Vss, is really at 1.5 V, the voltage difference upon which the TTL device acts is only 0.5 V which the TTL device will interpret as a "0" rather than as a "1".
To reduce the noise, one has to control di/dt. The inductance L of the package can also be reduced, but for a given type of package, the inductance L is a given.
Over the years, many solutions have been proposed to reduce and control di/dt. These solutions are based on the fact that the speed di/dt is limited by low Vcc voltage levels and high operating temperatures while the noise is limited by high Vcc voltage levels and low operating temperatures, where Vcc is the internal supply voltage. Each technique includes voltage and temperature compensation to minimize the variation between the ideal speed and noise operating conditions.
Alternatively, one can spread the noise as evenly as possible across the switching period by providing a constant di/dt. This is a very complex task.
One way to speed up the circuit for a given noise is to minimize the output swing either by not letting the output move to the full Vcc level or by forcing the output to an intermediate level during the read cycle while waiting for the correct data to arrive and then letting the output swing. The second option is illustrated in FIG. 1B to which reference is briefly now made.
FIG. 1B is a voltage-time graph illustrating two possible voltage curves for the gate of pull-down transistor 1 (FIG. 1A) when operating against a 100 pF load. One curve, labeled 2, has a constant voltage change (dV/dt) and the other curve, labeled 4, has an initial, steep rise 6 in voltage to a threshold level of the gate and a later, more gentle rise 8 to the final voltage level. Gentle rise 8 may be produced with a function such as .sqroot.V.sub.G -V.sub.T . The noise signal corresponding to curves 2 and 4 are also shown and are labeled 7 and 9, respectively. The output signals corresponding to curves 2 and 4 are labeled 11 and 13, respectively.
Curve 4 utilizes the fact that, until the voltage on an n-channel transistor, such as pull-down transistor 1, reaches a threshold level, the transistor will not conduct current. Therefore, the current speed is negligible during the voltage rise to the threshold level and any rate of voltage rise will not affect the output noise.
Although the total amount of noise integrated over the period shown is the same, noise curve 9 is much more uniform and has a lower overall noise level than noise curve 7. Noise curve 9 is more desirable since the noise problem stems mostly from the maximum level of the noise rather than from its duration.
Output curve 13, corresponding to gate ramp 4, falls to the desired output value faster than does output curve 11. Therefore, gate ramp 4, which has the less noisy output, also has the faster speed.
The following articles describe the prior art:
"A 0.1-.mu.A Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM", by M. Ando, et al., GA Journal of Solid-State Circuits, Vol. 24, No. 6, December 1989, pp. 1708-1710; and
"Simple Noise Model and Low-Noise Data-Output Buffer for Ultrahigh-Speed Memories", by T. Whitey, et al., IEEE Journal of Solid-Sta Circuits, Vol. 25, No. 6, December 1990, pp. 1586-1588.
Any number of the prior art techniques can be utilized together to reduce the overall output noise and to improve the speed.